First In-First Out (FIFO) memory devices are used to solve many problems in electrical systems. One key use for FIFO's is as a speed matching buffer between two different time domains where one time domain is running at a different clock rate than another time domain, for example. Presently FIFO designs are made from SRAM cells. FIG. 1 depicts a conventional SRAM cell 100. Two back to back inverters (101, 103) act as the storage element of the cell 100 and two steering transistors (102, 104) serve as gating logic to the bit lines 106 and 107 that are denoted as Bit and Bit*, respectively. Bit and Bit* are used to pass data values during reads and writes to the cell 100. The logic value applied to the Bit line 106 is the inverse of the logic value applied to the Bit* line 107. The steering transistors (102, 104) are enabled by a Word_Line 109 that is electrically coupled with an address decoder (not shown) which activates the steering transistors (102, 104) by driving an appropriate logic value and/or voltage on word line 109, for example. The cell 100 depicted in FIG. 1 works well for SRAM applications, but falls short of the requirements needed for a FIFO. In a FIFO, both an input port and an output port need to be able to access memory locations in the FIFO (e.g., memory cells) at the same time, with the only limit being not to simultaneously access the same memory cell at the same time. To accomplish this, another access port is required, one for reading data from the FIFO and one for writing data to the FIFO.
Reference is now made to FIG. 2 where the aforementioned task is accomplished by adding another access set of transistors. In FIG. 2, a conventional SRAM cell 200 includes back to back inverters (201, 203) which serve as the storage element of the cell 200, steering transistors (202, 204) which are electrically coupled with Word_Line_A 209 and Bit_A and Bit_A* lines (205, 207), and steering transistors (206, 208) which are electrically coupled with Word_Line_B 215 and Bit_B and Bit_B* lines (211, 213). In cell 200, Word_Line_A 209 or Word_Line_B 215 can be activated for equal access of the memory holding register (back to back inverters 201 and 203). In the structure depicted in FIG. 2 the A port has access by enabling the A word line 209 and driving or sensing the A bit line pair (Bit_A 205 and Bit_A* 207) The B port, likewise, can get access by activating the B word line 215 and sensing the B bit line pair (Bit_B 211 and Bit_B* 213).
Turning now to FIG. 3, in a conventional FIFO architecture 300, data is input to a SRAM memory array 301 on one side and output from the array 301 on the other side. Each port has control signals for writing (Wr_F, Wr_WL) or reading (Rd_F, Rd_WL). Typical of the write port is a counter/decoder 303 that receives a write enable signal Wr_En and a write clock signal Wr_Clk. In some designs free running clocks are used and data is only clocked in when the write enable goes active. In other designs where the clock is gated, a write enable signal is held active, allowing the gated clock (e.g., strobe) to load incoming data. Subsequently, the incoming write data is loaded into memory at the location being pointed to by the word line. The word line is typically generated in 1 of 2 ways. The first way is to use a counter that drives a decoder (e.g., counter & decoder 303) that decodes a unique value (word line) for the counter value. The word line, in combination with the clock (e.g., Wr_CLK) and write enable (e.g., Wr_En) generates a pulse on the decoded word line (e.g., Wr_WL). The data resident on the bit lines are gated to the cell and drive the holding register (e.g., the aforementioned back-to-back inverters) to the desired state. The bit line being driven low is the key signal for determining if the data value for a logic “1” or a logic “0” is being written. A low on the Bit or Bit* will determine the value of data to be stored.
FIG. 4 depicts a more detailed path for writing data to a conventional FIFO. The schematic depicted in FIG. 4 is essentially the write portion of the schematic depicted in FIG. 3. As can be seen in FIG. 4, most designs operate with some sort of pre-charge circuitry. This can be done by several ways. The three transistors (418, 420, 422) connected between the bit lines (Bit_A, Bit_A*) perform this function. When a write command is received, as indicated by the interface control signals (Wr_En, Wr_Clk), a pre-charge pulse Wr_Pre_Charge is generated by counter 411. The Wr_Pre_Charge pulse turns on the three transistors (418, 420, 422) which drive each line (Bit_A, Bit_A*) to a positive voltage and the transistor 422 between the bit lines (Bit_A, Bit_A*) is turned on to equalize the values between the two bit lines (Bit_A, Bit_A*). With the pre-charge in place, one or more of the word lines (Wr_A0, Wr_A1, Wr_A2, . . . Wr_An) are enabled such that data values on Wr_Data are gated to one or more of the memory cells (421, 423, 425, . . . n) which store the values on the bit lines (Bit_A, Bit_A*). In many designs the pre-charge is on, forcing a pre-charge, and turned off at the start of the write, allowing data drivers to force their value.
The read functions much like the write. The interface is typically controlled by a read enable and a clock and the memory array outputs data from the memory array. The read data is accessed at the location pointed to by the read counter and read decoder, as was described above for the write function.
FIG. 5 depicts in greater detail the read path discussed above in FIG. 3. A read operation to the conventional FIFO activates the read enable Rd_En and the read clock Rd_Clk which starts a simple sequence in the memory. A read pre-charge Rd_Pre_Charge is generated that typically sets the bit lines (Bit_B, Bit_B*) to a high level using transistors 518 and 520 between bit lines (Bit_B, Bit_B*) and transistor 522 for equalization. One or more word lines (Rd_A0, Rd_A1, Rd_A2, . . . Rd_An) for the decoded address is then pulsed and contents of one or more cells (521, 523, 525, . . . n) are then gated out onto the read bit lines (Bit_B, Bit_B*). The value gated onto the bit lines (Bit_B, Bit_B*) is then sent to a sense amplifier 535 for amplification and then output from the device as the read data Rd_Data. Optionally, there may be a multiplexer 531 between the bit lines (Bit_B, Bit_B*) and the sense amplifier 535. This will be determined by array layout. If parallel cells are designed for a better aspect ratio, the decoders will decode this and steer the selected column to the sense amplifier. The pre-charge is active and then is turned off as the word line turns on. This will place the bit lines at a known starting point and the value read out will switch faster from the known center line, giving a faster readout.
The above described conventional FIFO implementations use counters and decoders as the addressing methodology. An alternate conventional FIFO implementation 600 is depicted in FIG. 6. In FIG. 6 a pair of ring counters 620 and 640 for a write path and read path respectively, are depicted. The ring counters (620, 640) act by passing a “1” around a register loop formed by a series of flip-flops that are clocked by Wr_Clk and Rd_Clk and enabled by Wr_En and Rd_En. The register loop with the “1” is pointing to a particular word line (Wr_A0, Wr_A1, Wr_A2, . . . Wr_An for the write path and Rd_A0, Rd_A1, Rd_A2, . . . Rd_An for the read path). Each register output is a word line enable for the write path (620) and the other ring counter acts as a word line enable for the read path (640) word lines. The conventional ring counter methodology typically requires more logic than the above described counter and decoder methodology, but it is faster as the shift time occurs faster than the counter decoder allowing for faster interface operation, back to back.
We have described data operations on conventional FIFO's. Now a few usage details will be described. At power up, the read and write counters or ring counters are initialized to the same vale. As depicted in FIG. 3, the FIFO 300 has compare logic 307 used for management between the two counters (303, 305). When the write and read address are the same the compare logic 307 will detect the identical addresses and output an empty signal Empty to a read interface (not shown) that is electrically coupled with Empty. This will be used by the read port to tell it that no data is valid in the FIFO 300 and that no read should be done.
A Full flag electrically coupled with the write port will be inactive, indicating to the write port that it is ok to write into the memory. When a write occurs the write data is loaded into the first address and the counter increments. The two counters (303, 305) are now not equal and the empty signal Empty will go inactive. This tells the read port that valid data is present and can be read. When this data is read, the read counter is advanced. If no further write has occurred, then the two counters (303, 305) are equal and the empty flag Empty is again asserted and goes active. If the read port is busy and is not reading data the write port can continue to enter data. Data operations on the FIFO can continue until the write address is one (1) less than the read address (it has filled the FIFO and rolled over the address to start anew). Subsequently, the compare logic 307 will detect a full state in the FIFO 300 and activate the full flag Full. Activating the Full flag signals the write port to stop writing data. As soon as the read port reads the next address the FIFO will deactivate the Full flag and write operations are allowed to continue. A system using the conventional SRAM based FIFO can use these flags (Empty, Full) in the manner described to send data between two different time domains.
The conventional FIFO described above has served the market well, but it is based on the non-volatile SRAM cell design. Although SRAM cells are fast they require large die sizes, are non-volatile, and lose their data contents on loss of power. This complicates many applications and requires costly, heavy, and large battery backup systems to retain data after power loss. There are continuing efforts to improve FIFO technology.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the described drawings are not necessarily drawn to scale.